View ML2350CCP12_97840.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

May 1997
ML2340*, ML2350** Single Supply, Programmable 8-Bit D/A Converters
GENERAL DESCRIPTION
The ML2340 and ML2350 are CMOS voltage output, 8-bit D/A converters with an internal voltage reference and a P interface. These devices are designed to be powered by a single supply, although they can be powered from dual power supplies. The output voltage swings above zero scale (VZS) in the unipolar mode or around zero scale (VZS) in the bipolar mode, both with programmable gain. VZS can be set to any voltage from AGND to 2.25V below VCC. The digital and analog grounds, DGND and AGND, are totally independent of each other. DGND can be set to any voltage from AGND to 4.5V below VCC for easy interfacing to standard TTL and CMOS logic families. The high level of integration and versatility of the ML2340 and ML2350 makes them ideal for a wide range of applications in hard disk drives, automotive, telecom, and a variety of general purpose industrial uses. One specific intended application is controlling a hard disk voice coil. The internal reference of the ML2340 provides a 2.25V or 4.50V output for use with A/D converters that use a single 5V 10% power supply, while the ML2350 provide a 2.50V or 5.00V reference output.
FEATURES
s
Programmable output voltage gain settings of 2, 1, 1 /2, 1/4 provide 8-, 9-, 10-, or 11-bit effective resolution around zero AGND to VCC output voltage swing Bipolar or unipolar output voltage 4.5V to 13.2V single supply or 2.25V to 6.5V dual-supply operation Transparent latch allows microprocessor interface with 30ns setup time Data flow-through mode Voltage reference output ML2340 ........................................... 2.25V or 4.50V ML2350 ........................................... 2.50V or 5.00V Nonlinearity .................................... 1/4 LSB or 1/2 LSB Output voltage settling time over temperature and supply voltage tolerance Within 1V of VCC and AGND ................... 2.5s max Within 100mV of VCC and AGND ............... 5s max TTL and CMOS compatible digital inputs Low supply current (5V supply) ..................... 5mA max 18-pin DIP or surface mount SOlC
s s s s s s
s s
s s s
BLOCK DIAGRAM
VZS VREFOUT VREF VCC AGND
VREFIN 8-BIT D/A
- + OP AMP VOUT
DGND RESISTORS SWITCHES DECODERS
DATA LATCH
XFER
DB0 (LSB)
DB7 (MSB)
GAIN 0
GAIN 1
* This Part Is Obsolete ** This Part Is End Of Life As Of August 1, 2000
1
ML2340, ML2350
PIN CONNECTIONS
ML2340 ML2350 18-Pin DIP (P18)
VCC VOUT VZS AGND DGND DB0 DB1 DB2 DB3
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
ML2340 ML2350 18-Pin SOIC (S18W)
VCC VOUT VZS AGND DGND DB0 DB1 DB2 DB3
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
VREF IN VREF OUT GAIN 1 GAIN 0 XFER DB7 DB6 DB5 DB4
VREF IN VREF OUT GAIN 1 GAIN 0 XFER DB7 DB6 DB5 DB4
TOP VIEW
TOP VIEW
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1 2 3
VCC VOUT VZS
Positive supply. Voltage output of the D/A converter. VOUT is referenced to VZS. Zero Scale Voltage. VOUT is referenced to VZS. VZS is normally tied to AGND in the unipolar mode or to mid-supply in the bipolar mode. When the device is operated from a single power supply, VZS has a maximum current requirement of -300A in the bipolar mode. Analog ground. Digital ground. This is the ground reference level for all digital inputs. The range is AGND - DGND - VCC - 4.5V. DGND is normally tied to system ground. Data input -- Bit 0 (LSB). Data input -- Bit 1.
8 9
DB2 DB3
Data input -- Bit 2. Data input -- Bit 3. Data input -- Bit 4. Data input -- Bit 5. Data input -- Bit 6. Data input -- Bit 7 (MSB). Transfer enable input. The data is transferred into the transparent latch at the high level of XFER. Digital gain setting input 0. Digital gain setting input 1. Voltage reference output. VREF OUT is referenced to AGND. VREF OUT is set to 2.5V and 5.0V in a low-voltage and high-voltage operation, respectively for the ML2350; 2.25V and 4.5V for the ML2340. Voltage reference input. VREF IN is referenced to AGND.
10 DB4 11 DB5 12 DB6 13 DB7 14 XFER
4 5
AGND DGND
15 GAIN 0 16 GAIN 1 17 VREF OUT
6 7
DB0 DB1
18 VREF IN
2
ML2340, ML2350
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage VCC with Respect to AGND ............ 14.2V DGND ............................................ -0.3V to VCC + 0.3V VZS, VREF IN ................................................ -0.3V to VCC + 0.3V Logic Inputs .................................... -0.3V to VCC + 0.3V Input Current per Pin ............................................ 25mA Storage Temperature .............................. -65C to +150C Package Dissipation at TA = 25C (Board Mount) ... 875mW Lead Temperature (Soldering 10 sec.) Dual-In-Line Package (Molded) .......................... 260C Dual-In-Line Package (Ceramic) ......................... 300C Molded Small Outline IC Package Vapor Phase (60 sec.) ..................................... 215C Infrared (15 sec.) ............................................ 220C
OPERATING CONDITIONS
Supply Voltage, VCC .......................... 4.5VDC to 13.2VDC Temperature Range ML2350BIJ .......................................... -40C to +85C ML2340BCP, ML2340CCP ML2350BCP, ML2350CCP ML2340BCS, ML2340CCS ML2350BCS, ML2350CCS ..................... 0C to +70C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = Operating temperature range, VCC - AGND = 5V 10% and 12V 10%, VREF IN for ML2340 = 2.25V and 4.50V, for ML2350 VREF IN = 2.50V and 5.00V, VOUT load is RL = 1kW and CL = 100pF, VREF load is RL = 1kW and CL = 100pF and input control signals with tR = tF - 20ns. (Note 1)
ML2340XCX, ML2350XCX PARAMETER NOTES CONDITIONS MIN TYP MAX MIN ML2350XIX TYP MAX UNITS
Converter and Programmable Gain Amplifier Converter Resolution Integral Linearity Error ML2340BXX, ML2350BXX ML2340CXX, ML2350CXX Differential Linearity Error ML2340BXX, ML2350BXX ML2340CXX, ML2350CXX Mode Select Unipolar Output Bipolar Output Offset Error Unipolar Mode Bipolar Mode GAIN = 2, 1, 1/2, or 1/4 1/4 1/2 GAIN = 2, 1, 1/2, or 1/4 1/4 1/2 VZS with respect to AGND 0 1.50 Figure 1 GAIN = 1/4, 1/2, 1 GAIN = 2 Figure 1 GAIN = 1/4, 1/2, 1, 2 Figure 1 GAIN = 1/4, 1/2, 1, 2 GAIN = 1/4, 1/2, 1, 2 1.0 VCC-2.25 10 20 10 plus 21/2 LSB 0.5 0.5 2 2 0.5 0.5 0 1.50 1.0 VCC-2.25 12 24 10 plus 21/2 LSB 2.5 2.5 V V mV mV mV 1/4 1/2 LSB LSB 1/4 1/2 LSB LSB 8 8 Bits
Gain Error Unipolar Mode Bipolar Mode
%FS %FS
3
ML2340, ML2350
ELECTRICAL CHARACTERISTICS
PARAMETER Reference VREF OUT Voltage ML2340BXX VCC - 7.0V VCC * 8.0V ML2340CXX VCC - 7.0V VCC * 8.0V ML2350BXX VCC - 7.0V VCC * 8.0V ML2350CXX VCC - 7.0V VCC * 8.0V Temperature Coefficient VREF OUT VREF Output Current VREF OUT Power Supply Rejection Ratio VREF IN and VZS VREF IN Input Range VREF IN DC Input Resistance VZS Voltage Range Analog Output VOUT Output Swing Unipolar Mode 2 RL = 100kW RL = 1kW Bipolar Mode RL = 100kW RL = 1kW VOUT Output Current Power Supply Rejection Ratio AGND+1V(Continued)
ML2340XCX, ML2350XCX ML2350XIX MIN TYP MAX UNITS MIN TYP MAX
CONDITIONS
50 5 0.75 -40
50
4
ML2340, ML2350
ELECTRICAL CHARACTERISTICS
PARAMETER Digital and DC VIN(0) Logical "0" Input Voltage VIN(1) Logical "1" Input Voltage IIN(0) Logical "0" Input Current IIN(1) Logical "1" Input Current Supply Current, Bipolar Mode ICC, VCC Current IAGND, Analog Ground Current IVZS, VZS Current ICC, VCC Current IAGND, Analog Ground Current IVZS, VZS Current Supply Current, Unipolar Mode ICC, VCC Current IAGND, Analog Ground Current IVZS, VZS Current ICC, VCC Current IAGND, Analog Ground Current IVZS, VZS Current AC Performance Settling Time tS1 tS2 Figure 2, Output Step of AGND + 1V to VCC - 1V, RL = 1kW Output Step of AGND + 100mV to VCC - 100mV, RL = 100kW Output Step of 1LSB Change of Any Gain Setting Figure 3 Figure 3 Figure 3 60 40 0 16 1.1 1.2 2.5 2.5 5 1.2 2.5 3.0 6 s s VIN = DGND VIN = VCC 2.0 -1 1 0.8 2.0 -1 1 0.8 V V A A NOTES
(Continued)
ML2340XCX, ML2350XCX ML2350XIX MIN TYP MAX UNITS MIN TYP MAX
CONDITIONS
VCC = 5V 10% -90 VCC = 12V 10% -90
5.3 -5.0 -300 9.3 -9.0 -300
5.3 -5.0 -300 9.3 -9.0 -300
mA mA A mA mA A
-90
-90
3
VCC = 5V 10%
6.0 -4.3 -1.7
6.0 -4.3 -1.7 11.0 -7.3 -3.7
mA mA mA mA mA mA
VCC = 12V 10% 3
11.0 -7.3 -3.7
tS3 tS4, Gain Change tXFER, XFER Pulse Width tDBS, DB0-DB7 Setup Time tDBH, DB0-DB7 Hold Time tRESET, Power-On Reset Time
Note 1: Note 2: Note 3:
1 2.5 60 45 0 1.1
1
s s ns ns ns
16
s
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Supply current and analog ground current are specified with the digital inputs stable and no load on VOUT. In unipolar operation with VZS and AGND tied together, digital codes that represent an analog value of less than 100mV from AGND should be avoided.
5
ML2340, ML2350
IDEAL WITH OFFSET
ACTUAL
GAIN ERROR IDEAL WITH OFFSET IDEAL ACTUAL ANALOG OUTPUT GAIN ERROR
OFFSET ERROR
ANALOG OUTPUT
OFFSET (ZERO) ERROR
IDEAL
DIGITAL INPUT
DIGITAL INPUT
Unipolar Mode Figure 1. Gain and Offset Error
Unipolar Mode
GAIN 0, GAIN 1
tS4 XFER
VOUT tS1, tS2, tS3
SETTLED TO 1/2 LSB
Figure 2. Settling Time
XFER tWR DB0-DB7 tDBS VALID DATA tDBH
Figure 3. Single Buffered Mode
6
ML2340, ML2350
1.0 FUNCTIONAL DESCRIPTION
1.1 D/A CONVERTER The D/A converter is implemented using an array of equal current sources that are decoded semi-linearly for the four most significant bits to improve differential linearity and to reduce output glitch around major carries. See Figure 4. The input voltage reference of the D/A converter is the difference between VREF IN and AGND. This difference voltage is converted to a reference current using an internal resistor to set up the appropriate current level in the D/A converter. The D/A converter output current is then converted to a voltage output by an output buffer and a resistive network. The matching among the on-chip resistors preserves the gain accuracy between these conversions. The D/A converter can be used in a multiplying mode by modulating the reference input within the specified VREF IN range.
VCC
4I
4I
4I
2I
I
I
4-BIT DIVIDER DACOUT DACOUT
Figure 4. D/A Converter Implementation
1.2 SINGLE-SUPPLY vs. DUAL-SUPPLY OPERATION ML2340 and ML2350 can be powered from a single supply ranging from 4.5V to 13.2V or dual supplies ranging from 2.25V to 6.6V. The internal digital and analog circuitry is powered between VCC and AGND. The range of DGND is AGND - DGND - VCC - 4.5V with the logic thresholds set between 0.8V and 2.0V above DGND (standard TTL logic level). The range of VZS is AGND - VZS - (VCC - 2.25V). 1.3 UNIPOLAR AND BIPOLAR OUTPUT VOLTAGE SWING ML2340 and ML2350 can operate in either unipolar or bipolar output voltage mode. Unipolar/bipolar mode selection is determined by comparing the zero scale voltage (VZS) of these devices to a precise internal reference that is referred to AGND. VZS is ideally the voltage that will be produced at the DAC voltage output when the digital input data is set to all "0's" Unipolar mode is selected when VZS is lower than 1.00 volt, and bipolar mode is selected when VZS is greater than 1.50 volts. 1.3.1 Unipolar Output Mode In the unipolar mode, VOUT swings above VZS. Ideally the 00000000 code results in an output voltage of VZS, and the 11111111 code results in an output voltage of VFS x 255/256, where VFS is the full-scale voltage determined by VREF IN and the gain setting.
1.3.2 Bipolar Output Mode In the bipolar mode, VOUT swings around VZS. The input data is in 2's complement binary format. Ideally, the 00000000 code results in an output voltage of VZS; the 10000000 code results in an output voltage of (VZS - VFS); and the 01111111 results in an output voltage of (VZS + VFS 127/128), where VFS is the full scale output voltage determined by VREF IN and the gain setting. 1.4 OUTPUT BUFFER AND GAIN SETTING The output buffer converts the D/A output current to a voltage output using a resistive network with proper gain setting determined by the GAIN 0 and GAIN 1 inputs. There are four possible gain settings for unipolar output voltage mode and bipolar output voltage mode as listed below: Unipolar Output Voltage Mode
Voltage Output Swing Relative to VZS VREF IN 1/4 VREF IN 1/2 VREF IN 1 VREF IN 2
GAIN 1 0 0 1 1
GAIN 0 0 1 0 1
GAIN
1 1
/4 /2
1 2
7
ML2340, ML2350
Bipolar Output Voltage Mode
GAIN 1 0 0 1 1 GAIN 0 0 1 0 1 GAIN
1 1
ML2350
Voltage OutputP-P VREF IN /8
1
/4 /2
VREF IN 1/4 VREF IN 1/2 VREF IN 1
Gain Setting
1
VREF = 2.50V with VCC - 7.0V Unipolar Bipolar 0 to 0.625V -0.3125V to +0.3125V 0 to 1.250V -0.6250V to +0.6250V 0 to 2.500V -1.2500V to +1.2500V
VREF = 5.0V with VCC * 8.0V Unipolar 0 to 1.25V 0 to 2.50V 0 to 5.00V Bipolar -0.625V to +0.625V -1.250V to +1.250V -2.500V to +2.500V -5.000V to +5.000V
1 2
/4 /2
1
The output buffer can source or sink as much as 10mA of current with an output voltage of at least 1V from either VCC or AGND. As the output voltage approaches VCC or AGND the current sourcing/sinking capability of the output buffer is reduced. The output buffer can still swing down to within 10mV of AGND and up to within 40mV of VCC with a 100kW load at VOUT to AGND in the unipolar operation. In the bipolar operation, the output buffer swing is limited to about 100mV from either rails. 1.5 VOLTAGE REFERENCE A bandgap voltage reference is incorporated on the ML2340 and ML2350. Two reference voltages can be produced by each device. An internal comparator monitors the power supply voltage to determine the selection of the reference voltage. A reference voltage of 2.25 volts on the ML2340 and 2.50 volts on the ML2350 is selected when the supply voltage is less than approximately 7.50 volts. Otherwise, a reference voltage of 4.50 volts and 5.00 volts is selected. To prevent the comparator from oscillating between the two selections, avoid operation with a power supply between 70 and 8.0 volts. The bandgap reference is trimmed for zero Temperature Coefficient (TC) at 35C to minimize output voltage drift over the specified operating temperature range. The internal reference is buffered for use by the DAC and external circuits. The reference buffer will source more than 5mA of current and sink more than 1mA of current. With VREF IN connected to VREF OUT, the following output voltage ranges of the DAC are obtained: ML2340
VREF = 2.25V with VCC - 7.0V Unipolar Bipolar 0 to 0.562V -0.281V to +0.281V 0 to 1.125V -0.562V to +0.562V 0 to 2.250V -1.125V to +1.125V 0 to 4.500V -2.250V to +2.250V VREF = 4.5V with VCC * 8.0V Unipolar 0 to 1.125V 0 to 2.250V 0 to 4.500V 0 to 9.000V Bipolar -0.562V to +0.562V -1.125V to +1.125V -2.250V to +2.250V -4.500V to +4.500V
1 2
0 to 5.000V -2.5000V to 0 to 10.00V +2.5000V
An external reference can alternatively be used on VREF IN to set the desired full scale voltage. The linearity of the D/A converter depends on the reference used, however. To insure integral linearity at an 8-bit level, a reference voltage of no less than 2V and no more than 7V (2.75V for operation with a low-voltage power supply) should be used. 1.6 DIGITAL INTERFACE The digital interface of the ML2340 and ML2350 consist of a transfer input (XFER) and eight data inputs, DB0 through DB7. The digital interface operates in one of the two modes: 1.6.1 Single-Buffered Mode Digital input data on DB0-DB7 is passed through an 8-bit transparent input latch on the rising edge of XFER. Because the outputs of the latch are connected directly to the inputs of the internal DAC, changes on the digital data while the XFER input is still active will cause an immediate change in the DAC output voltage. To hold the input data on the latch, the XFER input needs deactivated while the data is still stable. 1.6.2 Flow-Through Mode In the flow-through mode, the input latch is bypassed. When XFER is set to logic "1", a change of data inputs, DB0-DB7, results in an immediate update of the output voltage. 1.7 POWER-ON-RESET The ML2340 and ML2350 have an internal power-onreset circuit to initialize the device when power is first applied to the device. The power-on-reset interval of typically 8s begins when the supply voltage, V CC reaches approximately 2.0V. During the power-on-reset interval, the transparent latch is reset to all "0's".
Gain Setting
1
/4 /2
1
1 2
8
ML2340, ML2350
2.0 TYPICAL APPLICATIONS
+VREF ML2271 0 VIN 4.5V
4.5V
VREFOUT VREFIN ML2340 D/A WITH REFERENCE
P
VOUT
Figure 5. Using 4.50V Reference of D/A for Reference of A/D Using Single 5V VCC 10%
DB7 DB0 INT RD VIN ML2261
DATA
D7 D0 INT DEN
ADDRESS DECODE WR CS CLOCK SOURCE OR TIMER DB7 DB0 ML2340 D/A XFER
HEN TMS320 /E14 C15 PA0 PA1 PA2
VOUT
Figure 6. TMS320 Interface
+5V VCC ML2350 VOUT VREFIN VREFOUT VZS GAIN 0 AGND GAIN 1 VOUT, GAIN 2
5.0V - 100mV
UNIPOLAR VOUT 0 TO 5V 2.50V
256 CODES 2.5V 256 CODES 1.25V 256 CODES GND VOUT, GAIN 1 GND GND VOUT, GAIN 1/2
0.625V 256 CODES GND VOUT, GAIN 1/4
Figure 7. Single 5V Supply Unipolar VOUT
9
ML2340, ML2350
TYPICAL APPLICATIONS
(Continued)
+12V VCC ML2340 VOUT VREFIN VREFOUT VZS GAIN 0 AGND GAIN 1 VOUT, GAIN 2 BIPOLAR VOUT AROUND 4.5V 4.50V 256 CODES
9.0V
6.75V 256 CODES 4.5V 4.5V
5.625V 256 CODES 4.5V 3.375V VOUT, GAIN 1/2
5.062V 4.5V 256 CODES 3.938V VOUT, GAIN 1/4
2.25V VOUT, GAIN 1 GND + 100mV
Figure 8. Single 12V Supply, Bipolar VOUT with 11-Bits Resolution Around 4.5V
+12V
+5V +12V
VCC ML2340 17
2 0.1F
2
+12V
+5V PWR VC OUTPUT+
19 11 10 13 1
16 XFER DB0 VREF OUT 20 VREF IN VZS DB7 1 4 3 14 15 0.1F
REF
PWR GND A
RSENSE ML4406
8 SERVO COIL
MICROCONTROLLER
18 19
VOUT
GAIN 0 GAIN 1 AGND DGND 5 6
CONTROL+ OUTPUT- 12 CONTROL- 9 PWR GND B 3 DISABLE 6 GND POWERFAIL RETRACT HIGH/LOW 4 I(RET) SET R(RET) V(RET) 7
20 1 5
FROM MOTOR WINDINGS
Figure 9. Hard Disc Drive Servo Coil Driver Providing 13-Bit Effective Resolution
10
ML2340, ML2350
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P18 18-Pin PDIP
0.890 - 0.910 (22.60 - 23.12) 18
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.045 MIN (1.14 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S18 18-Pin SOIC
0.449 - 0.463 (11.40 - 11.76) 18
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.009 - 0.013 (0.22 - 0.33)
11
ML2340, ML2350
ORDERING INFORMATION
PART NUMBER VREF OUT = 2.25V with VCC = 5V ML2340CCP/5 (OBS) ML2340CCS/5 (OBS) VREF OUT = 2.50V with VCC = 5V ML2350CCP/5 (OBS) ML2350CCS/5 (EOL) ML2350CIS/5 (EOL) VREF OUT = 4.50V with VCC = 12V ML2340CCP/12 (OBS) ML2340CCS/12 (OBS) VREF OUT = 5.00V with VCC = 12V ML2350CCP/12 (OBS) ML2350CCS/12 (OBS) ML2350CIS/12 (OBS) 1/2 LSB 0C to 70C 0C to 70C -40C to 85C Molded DIP (P18) Molded SOIC (S18) Molded SOIC (S18) 1/2 LSB 0C to 70C 0C to 70C Molded DIP (P18) Molded SOIC (S18) 1/2 LSB 0C to 70C 0C to 70C -40C to 85C Molded DIP (P18) Molded SOIC (S18) Molded SOIC (S18) 1/2 LSB 0C to 70C 0C to 70C Molded DIP (P18) Molded SOIC (S18) INTEGRAL & DIFFERENTIAL NON-LINEARITY TEMPERATURE RANGE PACKAGE
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS2340_50-01
12

▲Up To Search▲

Price & Availability of ML2350CCP12

	To Download ML2350CCP12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .